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In order to select a right LDO, some key criteria are important to be considered: Vin(min), Vin(max), Vout, Iout, Power dissipation, dropout voltage, PSRR, Low Iq.
Here is the basic circuit of a PMOS LDO. It consists of a pass element Q1, a voltage reference and an error amplifier which controls the pass element. The error amplifier senses the output voltage via a resistor divider network.
In this drawing, the pass element is a P-channel MOSFET with the source connected to the input voltage. The control loop is simple: The error amplifier controls the P-MOSFET gate to keep the voltage at the feedback pin at the same level as the voltage reference. When the output voltage drops due to increased load or lower input voltage, the error amplifier lowers the gate voltage with respect to the source. This increases the conduction level of the P-MOSFET, and the output voltage rises again to the original regulated voltage. In this configuration, the MOSFET can be controlled very close to the MOSFET ON level, which makes it possible to operate VIN very close to VOUT. But since the gate cannot be pulled lower than ground level, the input voltage must be high enough to allow sufficient headroom for the MOSFET gate-source voltage. To ensure sufficient MOSFET gate drive voltage, LDO's with P-MOSFET pass elements normally have a minimum input voltage requirement of around 2.5V.
In some applications you may want to drive an LDO from a very low voltage supply rail. In these cases, you need to select an LDO with an N-channel MOSFET pass element. LDO's with N-channel MOSFET pass elements need to provide a gate drive which is higher than the output voltage. In order to make it possible to use very low input and output voltages, many N-MOSFET LDO's have a gate drive circuit that is supplied by an internal charge-pump or external bias voltage. This makes it possible to use these LDOs with very low input voltages, down to 1V.
N-MOSFETs also have better RDS(ON) than similar sized P-MOSFETs, so their drop-out voltage is also lower, making it possible to supply more current in low voltage drop applications. Below is an example of an NMOS LDO which provides a clean and stable 1.0V supply from a low 1.5V supply rail. Due to the low voltage drop of only 0.5V across the LDO, it can deliver more current without excessive dissipation.
Richtek provides LDOs with wide input voltage range up to 80V.However, high (Vin–Vout) drop will quickly lead to high LDO dissipation at moderate load currents. Because the LDO power dissipation is (Vin-Vout) * I_load, any high voltage difference will cause high power dissipation.
Fixed output voltage LDOs have the feedback network internally. Adjustable output LDOs use an external feedback network, which gives more flexibility. Some adjustable parts also have an internal feedback network, so they can be used as fixed output version as well.
The current capability relates directly to dropout voltage and power dissipation. Linear controllers use external MOSFETs which can have larger current capability.
• The power dissipation in the LDO is determined by the voltage drop (VIN-VOUT) across the LDO multiplied by the current passing through the LDO (IOUT), which can be calculated from the formula: PD = (VIN-VOUT) * ILOAD.
The below graph shows the allowed LDO voltage drop versus LDO current for specific power dissipation values.
Larger current or larger voltage drop across the LDO quickly leads to high device power dissipation. The LDO package needs to be able to handle this power dissipation.
Maximum allowed device power dissipation for SMD type LDOs depends on package, PCB layout and ambient temperature. You can calculate the allowed power dissipation by dividing the allowed temperature difference between junction and ambient by the thermal resistance between junction and ambient. The thermal resistance value θJA is shown in the datasheet, but keep in mind that this value is based on the JEDEC method, which can be slightly conservative.
Here are some practical power dissipation limits for various package types, based on a normal PCB layout with some extra copper connected to the package pins and thermal pad, a maximum PCB ambient temperature of 60°C, and maximum silicon die temperature of 125°C. If your ambient temperature is lower, the power dissipation can be higher. If your PCB is small, or there are other hot components nearby, the maximum power dissipation may be less.
LDOs are Low Dropout Linear regulators. It basically means that these devices can still regulate the output voltage, even when the input voltage is very close to the output voltage. LDO dropout voltage is defined as the voltage drop across the regulator where the device can no longer regulate the output voltage.
Here is the basic circuit of an LDO with a P-channel MOSFET pass device. The MOSFET source is connected to VIN. To regulate the output voltage, the error amplifier controls the P-MOSFET gate voltage with respect to VIN, thereby controlling the MOSFET conduction level.
The LDO needs a certain amount of input to output voltage difference for regulation. When the difference between input and output voltage becomes smaller, the MOSFET operation shifts toward the MOSFET Ohmic region toward the left in the MOSFET I/V curves. In the Ohmic region, the MOSFET becomes resistive, and the error amplifier will pull the gate near ground level. At that point, the output voltage cannot be regulated anymore.
To maintain a well-regulated LDO output voltage, you should make sure that the input voltage including ripple and tolerances is always higher than the output voltage + LDO dropout voltage. Dropout curves as below in the LDO datasheet show this dropout voltage as a function of output current and temperature. These I/V curves basically represent the RDS(ON) of the pass MOSFET.
PSRR stands for power supply ripple rejection. The LDO PSRR value quantifies how well the LDO can reject input supply ripple at a certain frequency to keep the output voltage free of noise and ripple. In Richtek datasheets, PSRR is defined as the ripple attenuation ratio VOUT/VIN, therefore lower PSRR values are better.
The diagram shows the example of PSRR vs. frequency. At frequencies up to 10kHz, LDOs have high open loop gain, and can reject input ripple very well.
When frequency increases, the loop gain reduces due to the bandwidth limit of the LDO, and the PSRR curves rise. Higher LDO load pushes the load pole upwards, so the unity gain frequency at high load is also higher. In this example the LDO unity gain frequency is 300kHz at light load and 1MHz at high load, as can be seen from the peaks in the graph.
Above the unity gain frequency, the LDO is not able to actively remove ripple. The ripple attenuation at these very high frequencies is mostly caused by the LDO output capacitor and the LDO internal parasitic impedance.
The applications often run in sleep mode most of time and are only active for a short period of time. To minimize the power consumption in sleep mode, you need to select products with very low quiescent current (Iq). The LDO quiescent current is the current that is consumed by the IC internal feedback control and drive circuits. It is normally measured by measuring the current that flows out of the LDO ground pin.
Richtek ultra low IQ LDOs provide dynamic quiescent current control for obtaining the best performance in battery powered applications requiring long battery life and good dynamic load performance. The Low IQ LDO RT9063 provides a stable 2.8V supply to the micro controller, and the LDO ground current stays relatively constant at 1µA in the low load range, thereby prolonging battery life.
But at higher load currents, the ground current increases to improve the dynamic behavior of the LDO; when a sudden high load is encountered, the internal control circuit uses more energy to ensure a tight regulation of the output voltage.